1. Field of the Invention
The present invention relates to a power amplifier that is capable of adjusting an operating point and, more specifically, to a power amplifier that is capable of adjusting an operating point, in which bias voltage to be supplied to a control electrode of a power amplifying element that constitutes the power amplifier is varied in phase and adjusting gain of the power amplifier corresponding to variations in bias voltage.
2. Description of the Related Art
In the related art, in a Wireless LAN, standardized specifications for wireless transmitting/receiving signals are established by IEEE (Institute of Electrical and Electronics Engineers). In this case, in one of the standardized specifications, IEEE802.11a, specifies that the type of the wireless transmitting/receiving signal is OFDM (Orthogonal Frequency Division Multiplexing) system, and a system in which a primary modulation varies from BPSK (Binary Phase Shift Keying) of 6 Mbps to 64 QAM (Quadrature Amplitude Modulation) of 54 Mbps by every transmission rate (transmission capacity), and specifies an allowable value of modulation accuracy (EVM) as a linear performance standard of the wireless transmitting/receiving signal by each transmission rate. For example, when the transmission rate is 6 Mbps, the allowable value is −5 dB (EVM=56.2%). On the other hand, the higher the transmission rate, the severer the allowable value becomes, and thus when the transmission rate is 54 Mbps, only −25 dB (EVM=5.6%) is allowed. In this case, the transmission rates include 8 transmission rates of 6 Mbps, 9 Mbps, 12 Mbps, 18 Mbps, 24 Mbps, 36 Mbps, 48 Mbps, and 54 Mbps, and the transmission rate is selected depending on the distance to the person on the other end of the line, that is, electric field strength.
Generally, the fact that the linear performance of the wireless transmitting signal is determined mainly by the characteristics of the transmitting signal output amplifier (power amplifier) is known, and the fact that unnecessary signal components such as AM-AM conversion components or AM-PM conversion components are generated in the power amplifier when the linear performance of the power amplifier is not satisfactory, and such unnecessary signal components may cause deterioration of EVM is also known.
Therefore, it is also known that when designing a power amplifier that satisfies standards of IEEE802.11a, the power amplifier is required to have a linear performance that satisfies the allowable value of EVM when the transmission rate is high and the output power is required to have a high-output power characteristic within the allowable value of EVM, and that such characteristics may be satisfied by applying Class A bias on the power amplifier and flowing a relatively large operating current.
On the other hand, the Wireless LAN includes a miniature PCI (Programmable Communication Interface) card type integrated in a laptop computer, or PCMCIA (Personal Computer Memory Card International Association) type that can be externally inserted. However, since both types of Wireless LAN are supplied with operating power from a battery in the personal computer body. Therefore, when power consumption of the Wireless LAN increases, battery life of the personal computer body is shortened correspondingly. In this manner, although obtaining a satisfactorily linear performance characteristic contradicts reducing power consumption, the power amplifier in the Wireless LAN is basically desired to have low power consumption property that power consumption does not exceed a limit value and shortening of battery life is prevented.
FIG. 5 is a circuit diagram showing an example of the structure of a known transmitting signal output amplifier (power amplifier) in Wireless LAN, and showing an example in which a power amplifying stage includes independent elements.
As shown in FIG. 5, the power amplifier includes a power amplifying stage 51 and a bias control circuit 52. In this case, the power amplifying stage 51 includes a power amplifying transistor 53, a radio-frequency signal input terminal 54, a radio-frequency signal output terminal 55, and a load inductor 56. The bias control circuit 52 includes a first control transistor 57, a second control transistor 58, a power amplification stage drive signal (PA/ON) input terminal 59, an output inductor 60, and a power source terminal 61.
In the power amplifying stage 51, the power amplifying transistor 53 is connected in such a manner that a base is connected to a radio-frequency signal input terminal 54 trough a coupling capacitor (not designated by a numeral), and an emitter is grounded, and a collector is connected to a radio-frequency signal output terminal 55 through a coupling capacitor (not designated by a numeral). On the other hand, in the bias control circuit 52, the fist control transistor 57 is connected in such a manner that a base is connected to the power amplification stage drive signal input terminal 59 through an input resistance (not designated by a numeral), an emitter is grounded, and a collector is connected to a base of the second control transistor 58 through a resistance (not designated by a numeral). The second control transistor 58 is connected in such a manner that an emitter is connected to the power source terminal 61 through a resistance (not designated by a numeral) and a collector is connected to a base of the power amplifying transistor 53 through the output inductor 60.
The power amplifier constructed as described above acts as follows.
When a positive-level power amplification stage drive signal (PA/ON) is supplied to the power amplification stage drive signal input terminal 59, the power amplification stage drive signal is supplied to the first control transistor 57 and hence the first control transistor 57 is turned ON. When the first control transistor 57 is turned ON, the base of the second control transistor 58 is shifted to a negative level, and hence the second control transistor 58 is turned ON. When the second control transistor 58 is turned ON, a base bias voltage is supplied to the base of the power amplifying transistor 53 through the output inductor 60, and the power amplifying transistor 53 is brought into an actuating state. When a radio-frequency signal is supplied to the radio-frequency signal input terminal 54 at this moment, the power of the radio-frequency signal is amplified by the power amplifying transistor 53, and the amplified radio-frequency signal is supplied to the radio-frequency signal output terminal 55.
On the other hand, when a zero-leveled power amplification stage drive signal (PA/ON) is supplied to the power amplification stage drive signal input terminal 59, the first control transistor 57 is turned OFF by the power amplification stage drive signal. When the first control transistor 57 is turned OFF, the base of the second control transistor 58 is shifted into a positive level, and the second control transistor 58 is also turned OFF. When the second control transistor 58 is turned OFF, supply of a base bias voltage to the base of the power amplifying transistor 53 is stopped, and hence the power amplifying transistor 53 is brought into a nonaction state. Even when a radio-frequency signal is supplied to the radio-frequency signal input terminal 54 at this moment, the radio-frequency signal is blocked at the power amplifying transistor 53, no signal is supplied to the radio-frequency signal output terminal 55.
FIG. 6 is a circuit diagram showing another example of the construction of a known transmitting signal output amplifier (power amplifier) in Wireless LAN, showing an example in which the power amplifying stage is constructed of a Microwave Monolithic Integrated Circuit (MMIC).
In FIG. 6, the same components as those shown in FIG. 5 are designated by the same reference numerals.
The example shown in FIG. 6 differs from the example shown in FIG. 5 in that a MMIC 53(1) is used instead of the power amplifying transistor 53 in the power amplifying stage 51, and two output resistances 60(1), 60(2) are used in the bias control circuit 52 instead of the output inductor 60. Other constructions are the same as the example shown in FIG. 5.
In this case, the MMIC 53(1) is connected to the radio-frequency signal input terminal 54 through a coupling capacitor (not designated by a numeral) at an input end, and to the radio-frequency signal output terminal 55 through a coupling capacitor (not designated by a numeral) at an output end. The second control transistor 58 is connected at the collector to bias supply ends VD1, VD2 of the MMIC 53(1) through two output resistances 60(1), 60(2).
The action of the power amplifier constructed as described above is basically the same as the action of the power amplifier shown in FIG. 5. When a positive level power amplification stage drive signal (PA/ON) is supplied to the power amplification stage drive signal input terminal 59, the first control transistor 57 is turned ON and hence the second control transistor 58 is also turned ON. When the second control transistor 58 is turned ON, a bias voltage is supplied to the bias supply ends VD1, VD2 of the MMIC 53(1) through the two output resistances 60(1), 60(2), and hence the MMIC 53(1) is brought into the actuating state. When a radio-frequency signal is supplied to the radio-frequency signal input terminal 54 at this moment, the power of the radio-frequency signal is amplified by the MMIC 53(1), and the amplified radio-frequency signal is supplied to the radio-frequency signal output terminal 55.
On the other hand, when a zero-level power amplification stage drive signal (PA/ON) is supplied to the power amplification stage drive signal input terminal 59, the first control transistor 57 is turned OFF and the second control transistor 58 is also turned OFF. When the second control transistor 58 is turned OFF, supply of a bias voltage to the bias supply ends VD1, VD2 of the MMIC 53(1) is stopped, and hence the MMIC 53(1) is brought into a nonaction state. Even when a radio-frequency signal is supplied to the radio-frequency signal input terminal 54 at this moment, the radio-frequency signal is blocked at the MMIC 53(1), and no signal is supplied to the radio-frequency signal output terminal 55.
Each of the known power amplifiers described above is operated at a constant bias voltage irrespective of the transmission rate used and, more specifically, when the transmission rate is 6 Mbps, Class AB bias voltage is provided within a range that power consumption of the power amplifying transistor 53 or the MMIC 53(1) does not exceed the limit value, so that the maximum output can be obtained within the allowable range of the output power. Therefore, when the transmission rate reaches to a high transmission rate such as 48 Mbps or 54 Mbps, it is constrained by the linear performance standard, and the output voltage is reduced (backed off) to the value lower than that obtained when the transmission rate is 6 Mbps to operate at a low output power. Therefore, when comparing the output power obtained when the transmission rate is 6 Mbps with the output power obtained when the transmission rate is 54 Mbps, there is a difference in the order of 6 to 7 dB.
On the other hand, when the bias of the power amplifying transistor 53 or the MMIC 53(1) to be obtained when the transmission rate of 6 Mbps is switched from Class AB to Class AB close to Class A in order to increase the output power obtained when the transmission rate is 54 Mbps, power consumption when the transmission rate is 6 Mbps increases, and comes near or exceeds the limit value.
In contrast, when the bias of the power amplifying transistor 53 or the MMIC 53(1) to be obtained when the transmission rate is 6 Mbps is switched from Class AB to Class AB close to Class B in order to reduce power consumption obtained when the transmission rate is 6 Mbps, it is subjected to constraint of the linear performance standard unless the output power obtained when the transmission rate is 54 Mbps is further reduced.